High-Level Synthesis For Fpga, Part 3 - Advanced

Logic Design with Vitis-HLS
What you'll learn
Using Multi-Cycle design flow to develop sequential circuits in HLS.
Implementing stream communication and computation in HLS
Using FIFO as the synchronisation mechanism between to connected module
Learning how to use an array variable inside an HLS code
Connecting and AND HLS IP to BRAMs in a Vivado project
Working with pointers in HLS
Working with AXI protocol in HLS
Loop pipelining optimisation in HLS
Loop unrolling optimisation in HLS
Loop flattening optimisation in HLS
Loop rewinding optimisation in HLS
Working with the HLS-Stream library in HLS
Handshaking protocol and interfaces in HLS
Requirements
Understanding the basic concepts of C/C++ coding
Understanding the basic concepts of logic operators (e.g., AND, OR, XOR, SHIFT )
"High-Level Synthesis for FPGA, Part 1-Combinational Circuits" Udemy course
"High-Level Synthesis for FPGA, Part 2 - Sequential Circuits" Udemy course
BASYS3 evaluation board
Xilinx Vitis-HLS and Vivado (download Vivado ML Edition or Vivado Design Suite - HLx Editions for Windows or Linux)
Description
This course covers advanced topics in high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design. It quickly becomes a must-have skill for every hardware or software engineer keen on utilising FPGAs for their exceptional performance and low power consumption.This course is the first to explain the advanced HLS design flow topics. It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises to practice and master the proposed methods and approaches.This course is the third of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on multi-cycle design, advanced design, and optimisation techniques in HLS, the other courses in the series explain how to use single-cycle design techniques to develop combinational and sequential logic circuits in HLS.
Overview
Section 1: Prologue
Lecture 1 Introduction
Lecture 2 Course Structure
Section 2: LAB Setup
Lecture 3 Introduction
Lecture 4 Windows Instullation
Lecture 5 Linux Installation
Section 3: Multi-Cycle Design
Lecture 6 Introduction
Lecture 7 Definition
Lecture 8 Multi-Cycle Design vs SCII
Lecture 9 Example
Lecture 10 Handshaking
Lecture 11 Example with vld
Lecture 12 Example with ack
Lecture 13 Example with hs
Lecture 14 Block-Level Handshake
Lecture 15 Exercises
Section 4: Streaming
Lecture 16 Introduction
Lecture 17 Definition
Lecture 18 Streaming FIFO
Lecture 19 Streaming in HLS
Lecture 20 Streaming Example: Vitis-HLS
Lecture 21 Streaming Example: Vivado
Lecture 22 Exercises
Section 5: ArrayInHLS
Lecture 23 Introduction
Lecture 24 Definition
Lecture 25 Array Issues
Lecture 26 BRAM
Lecture 27 Array Read/Write: VitisHLS
Lecture 28 Array Read/Write: Vivado
Lecture 29 Exercises
Section 6: Pointers
Lecture 30 Introduction
Lecture 31 Definition
Lecture 32 Native Pointer Casting
Lecture 33 Pointers on the Interface
Lecture 34 Pointer Arithmetic
Lecture 35 Multi-Access Pointers on the Interface
Lecture 36 Exercises
Section 7: AXI in HLS
Lecture 37 Introduction
Lecture 38 Memory Mapped Interface
Lecture 39 AXI Protocol
Lecture 40 Memory Mapped Output 01
Lecture 41 AXI Addressing in Vivado
Lecture 42 Memory Mapped Output 02
Lecture 43 Memory Mapped I/O
Lecture 44 The m-axi interface
Lecture 45 Exercises
Section 8: Loops In HLS
Lecture 46 Introduction
Lecture 47 Definition
Lecture 48 Loop Unrolling
Lecture 49 Piplelining
Lecture 50 Failure to Pipeline
Lecture 51 (Waveform) Rewinding Pipelined Loops
Lecture 52 Exercises
Section 9: HLS Stream Library
Lecture 53 Introduction
Lecture 54 Definition
Lecture 55 Stream on the Interface
Lecture 56 Blocking/NonBlocking
Lecture 57 HLS Stream Dataflow
Lecture 58 Exercises
Hardware engineers,Software engineers who are interested in FPGAs,Lecturers, researchers, and professors who want to use FPGA-based HLS in lectures, courses or research,Digital Logic enthusiasts




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