Synopsys CoreTools vY-2026.03 Linux

Software Overview

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Synopsys coreTools provides a structured environment for packaging and integrating semiconductor intellectual property. The tool family is designed to capture IP knowledge and design intent, expose configuration options, assemble configured components, and provide information needed for subsequent design and verification tasks.
coreBuilder is a packaging tool for capturing the knowledge and design intent of IP. It supports graphical or command-based configuration menus and packages the different model views required by engineering teams. Packages created with coreBuilder are designed to comply with the IP-XACT specification.
coreAssembler is an IP assembly tool that generates configured RTL and interconnect information while documenting block and system configuration details. When used with coreBuilder, it can support the creation of configurable coreKits and generate a starting testbench configuration for design validation. It also generates IP-XACT XML for the assembled design.
coreConsultant provides utilities for configuring, implementing, and validating individual IP blocks packaged with coreBuilder. It can also generate IP-XACT XML for the corresponding IP block.
Key Features

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• IP packaging and integration for knowledge-based design and verification flows
• Capture IP knowledge and design intent with coreBuilder
• Graphical and command-based IP configuration menus
• Packaging of multiple IP model views
• IP-XACT-compliant packaging with coreBuilder
• IP assembly and configuration with coreAssembler
• Automatic generation of configured RTL and interconnect information
• Documentation of block and system configuration details
• Generation of starting testbench configurations
• Generation of IP-XACT XML for assembled designs
• Creation of configurable coreKits when combined with coreBuilder
• Configuration, implementation, and validation of individual IP blocks with coreConsultant
• Generation of IP-XACT XML for individual IP blocks

Why Choose Synopsys CoreTools

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Synopsys CoreTools provides separate utilities for packaging, assembling, configuring, and validating semiconductor IP within an integrated design flow. This organization allows engineering teams to manage IP configuration information and integration tasks in a structured manner.
The use of IP-XACT-based information exchange also supports standardized representation of IP and design configuration data. The tools are intended for semiconductor engineering environments where reusable IP and subsystem integration are central parts of the design process.
What's New

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The provided release information identifies this package as coreTools vY-2026.03. No detailed changelog or feature-specific release notes were provided in the source material.
System Requirements

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Linux *
Home Page

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Product Information

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• Software Name: coreTools
• Version: vY-2026.03
• Architecture: x86_64
• Languages: english
• License type: Full Version
• File Size: 1.0 Gb